Chapter 11: Serial Interfacing Embedded Systems - Shape The World Jonathan Valvano and Ramesh Yerraballi This chapter provides an introduction to serial interfacing, which means we send one bit at time. Serial communication is prevalent in both the computer industry in general and the embedded industry in specific. There are many serial protocols, but in this course we will show you one of the first and simplest protocols that transmit one bit at a time. We will show the theory and details of the universal asynchronous receiver/transmitter (UART) and then use it as an example for developing an I/O driver.

1. Serial Data Cable
2. Very-large-scale Integration

We will use busy-wait to synchronize the software with the hardware. Learning Objectives:. I/O synchronization. Models of I/O devices (busy, done, off).

Learn how to program the UART. Build a distributed system by connecting two systems together. Learn how to convert between numbers and ASCII strings Video 11.0.

Introduction to Serial Communication 11.1. I/O Synchronization Before we begin define serial communication, let's begin by introducing some performance measures.

The transmission speed, data width, parity, and flow control are all configurable and must be set the same for both UART correspondents. Figure 2 show the data framing for a transmission. Absent communication, the line is held high to indicate that it and the transmitter are not damaged. A transaction begins with a low start bit. The CDP6402 (Harris Semiconductors, RS 630-689) is a CMOS Universal Asynchronous Receiver/Transmitter for interfacing to asynchronous serial data channels. Its serial data format is programmable. It can have 5, 6, 7, or 8 bit length. The parity check can be odd, even or none. Stop bits can be 1, 1.5 or 2.

As engineers and scientists we are constantly making choices as we design new product or upgrade existing systems. A performance measure is a quantitative metric that the goodness of the system. The metrics and synchronization algorithms presented in this section will apply to all I/O communication. Latency is the time between when the I/O device indicated service is required and the time when service is initiated. Latency includes hardware delays in the digital hardware plus computer software delays. For an input device, software latency (or software response time) is the time between new input data ready and the software reading the data. For an output device, latency is the delay from output device idle and the software giving the device new data to output.

In this book, we will also have periodic events. For example, in our data acquisition systems, we wish to invoke the analog to digital converter (ADC) at a fixed time interval. In this way we can collect a sequence of digital values that approximate the continuous analog signal. Software latency in this case is the time between when the ADC conversion is supposed to be started, and when it is actually started. The microcomputer-based control system also employs periodic software processing. Similar to the data acquisition system, the latency in a control system is the time between when the control software is supposed to be run, and when it is actually run. A real-time system is one that can guarantee a worst case latency.

In other words, the software response time is small and bounded. Furthermore, this bound is small enough to satisfy overall specification of the system, such as no lost data.

Throughput or bandwidth is the maximum data flow in bytes/second that can be processed by the system. Sometimes the bandwidth is limited by the I/O device, while other times it is limited by computer software.

Bandwidth can be reported as an overall average or a short-term maximum. Priority determines the order of service when two or more requests are made simultaneously. Priority also determines if a high-priority request should be allowed to suspend a low priority request that is currently being processed. We may also wish to implement equal priority, so that no one device can monopolize the computer. In some computer literature, the term 'soft-real-time' is used to describe a system that supports priority.

The purpose of our interface is to allow the microcontroller to interact with its external I/O device. One of the choices the designer must make is the algorithm for how the software synchronizes with the hardware. There are five mechanisms to synchronize the microcontroller with the I/O device.

Each mechanism synchronizes the I/O data transfer to the busy to done transition. The methods are discussed in the following paragraphs. Synchronization Mechanisms Video 11.1. Device Communication requires Synchronization Blind cycle is a method where the software simply waits a fixed amount of time and assumes the I/O will complete before that fixed delay has elapsed.

For an input device, the software triggers (starts) the external input hardware, waits a specified time, then reads data from device. Blind cycle synchronization for an input device is shown on the left part of Figure 11.1.

For an output device, shown on the left part of Figure 11.2, the software writes data to the output device, triggers (starts) the device, then waits a specified time. We call this method blind, because there is no status information about the I/O device reported to the software. It is appropriate to use this method in situations where the I/O speed is short and predictable.

We can ask the LCD to display an ASCII character, wait 37 µs, and then we are sure the operation is complete. This method works because the LCD speed is short and predictable. Another good example of blind-cycle synchronization is spinning a stepper motor. If we repeat this 8-step sequence over and over 1) output a 0x05, 2) wait 1ms, 3) output a 0x06, 4) wait 1ms, 5) output a 0x0A, 6) wait 1ms, 7) output a 0x09, 8) wait 1ms, the motor will spin at a constant speed. The output device sets a flag when it has finished outputting the last data. Interactive Tool 11.1 Use the following tool to see how blind-cycle synchronization works.

You will need to enter a number between 1-10 to simulate the timing behavior of the device. Enter an amount of time to wait (1-10): Busy Wait is a software loop that checks the I/O status waiting for the done state. For an input device, the software waits until the input device has new data, and then reads it from the input device, see the middle parts of Figures 11.1 and 11.2. For an output device, the software writes data, triggers the output device then waits until the device is finished.

Another approach to output device interfacing is for the software to wait until the output device has finished the previous output, write data, and then trigger the device. Busy-wait synchronization will be used in situations where the software system is relatively simple and real-time response is not important. The UART software in this chapter will use busy-wait synchronization. Interactive Tool 11.2 Use the following tool to see how busy-wait synchronization works.

You will press the 'Ready' button to simulate the device being ready. Click to simulate I/O device becoming ready. An interrupt uses hardware to cause special software execution. With an input device, the hardware will request an interrupt when input device has new data.

The software interrupt service will read from the input device and save in global RAM, see the right parts of Figures 11.1 and 11.2. With an output device, the hardware will request an interrupt when the output device is idle. The software interrupt service will get data from a global structure, and then write to the device. Sometimes we configure the hardware timer to request interrupts on a periodic basis. The software interrupt service will perform a special function. A data acquisition system needs to read the ADC at a regular rate. Interrupt synchronization will be used in situations where the system is fairly complex (e.g., a lot of I/O devices) or when real-time response is important.

Interrupts will be presented in Chapter 12. Interactive Tool 11.3 Use the following tool to see how interrupt-based synchronization works. The foreground thread and background thread (the Interrupt Service Routine or ISR) communicate using a buffer called a first in first out queue (FIFO). Periodic Polling uses a clock interrupt to periodically check the I/O status. At the time of the interrupt the software will check the I/O status, performing actions as needed.

With an input device, a ready flag is set when the input device has new data. At the next periodic interrupt after an input flag is set, the software will read the data and save them in global RAM. With an output device, a ready flag is set when the output device is idle. At the next periodic interrupt after an output flag is set, the software will get data from a global structure, and write it. Periodic polling will be used in situations that require interrupts, but the I/O device does not support interrupt requests directly. DMA, or,direct memory access, is an interfacing approach that transfers data directly to/from memory. With an input device, the hardware will request a DMA transfer when the input device has new data.

Without the software’s knowledge or permission the DMA controller will read data from the input device and save it in memory. With an output device, the hardware will request a DMA transfer when the output device is idle. The DMA controller will get data from memory, and then write it to the device. Sometimes we configure the hardware timer to request DMA transfers on a periodic basis. DMA can be used to implement a high-speed data acquisition system. DMA synchronization will be used in situations where high bandwidth and low latency are important.

DMA will not be covered in this introductory class. For details on how to implement DMA on the LM4F120/TM4C123, see. One can think of the hardware being in one of three states. The idle state is when the device is disabled or inactive. No I/O occurs in the idle state. When active (not idle) the hardware toggles between the busy and ready states. The interface includes a flag specifying either busy (0) or ready (1) status.

Hardware-software synchronization revolves around this flag: The hardware will set the flag when the hardware component is complete. The software can read the flag to determine if the device is busy or ready. The software can clear the flag, signifying the software component is complete.

This flag serves as the hardware triggering event for an interrupt. For an input device, a status flag is set when new input data is available. The “busy to ready” state transition will cause a busy-wait loop to complete, see middle of Figure 11.1. Once the software recognizes the input device has new data, it will read the data and ask the input device to create more data. It is the busy to ready state transition that signals to the software that the hardware task is complete, and now software service is required.

When the hardware is in the ready state the I/O transaction is complete. Often the simple process of reading the data will clear the flag and request another input.

The problem with I/O devices is that they are usually much slower than software execution. Therefore, we need synchronization, which is the process of the hardware and software waiting for each other in a manner such that data is properly transmitted. A way to visualize this synchronization is to draw a state versus time plot of the activities of the hardware and software. For an input device, the software begins by waiting for new input. When the input device is busy it is in the process of creating new input.

When the input device is ready, new data is available. When the input device makes the transition from busy to ready, it releases the software to go forward. In a similar way, when the software accepts the input, it can release the input device hardware. The arrows in Figure 11.3 represent the synchronizing events. In this example, the time for the software to read and process the data is less than the time for the input device to create new input.

This situation is called I/O bound, meaning the bandwidth is limited by the speed of the I/O hardware. The software must wait for the input device to be ready (I/O bound input interface). If the input device were faster than the software, then the software waiting time would be zero.

This situation is called CPU bound (meaning the bandwidth is limited by the speed of the executing software). In real systems the bandwidth depends on both the hardware and the software. Another characteristic of real systems is the data can vary over time, like car traffic arriving and leaving a road intersection. In other words, the same I/O channel can sometimes be I/O bound, but at other times the channel could be CPU bound. We can store or buffer data in a first in first out (FIFO) queue, see Figure 11.4, while passing the data from one module to another. These modules may be input devices, output devices or software.

Because the buffer separates the generation of data from the consumption of data, it is very efficient, and hence it is prevalent in I/O communication. In particular, it can handle situations where there is an increase or decrease in the rates at which data is produced or consumed. Other names for this important interfacing mechanism include bounded buffer, producer-consumer, and buffered I/O. Data are entered into the FIFO as they arrive; we call Put to store data in the FIFO. Data are removed as they leave; we call Get to remove data from the FIFO. The FIFO maintains the order of the data, as it passes through the buffer.

We can think of a FIFO like a line at the post office. There is space in the lobby for a finite number of people to wait. As customers enter the post office they get in line at the end (put onto FIFO). As the postal worker services the customers, people at the front leave the line (get from the FIFO). It is bad situation (a serious error) if the waiting room becomes full and there is no room for people to wait (full FIFO). However, if there are no customers waiting (empty FIFO) the postal worker sits idle. An empty FIFO may be inefficient, but it is not considered an error.

A FIFO queue can be used to pass data from a producer to a consumer. At any given time there can be a variable number of elements stored in the FIFO. The order in which data are removed is the same as the order the data are entered. The busy-wait method is classified as unbuffered because the hardware and software must wait for each other during the transmission of each piece of data. The interrupt solution (shown in the right part of Figure 11.1) is classified as buffered, because the system allows the input device to run continuously, filling a FIFO with data as fast as it can.

In the same way, the software can empty the buffer whenever it is ready and whenever there is data in the buffer. The buffering used in an interrupt interface may be a hardware FIFO, a software FIFO, or both hardware and software FIFOs. We will see the FIFO queues will allow the I/O interface to operate during both situations: I/O bound and CPU bound. For an output device, a status flag is set when the output is idle and ready to accept more data.

The “busy to ready” state transition causes a busy-wait loop to complete, see the middle part of Figure 11.2. Once the software recognizes the output is idle, it gives the output device another piece of data to output. It will be important to make sure the software clears the flag each time new output is started. Figure 11.5 contains a state versus time plot of the activities of the output device hardware and software. For an output device, the software begins by generating data then sending it to the output device.

When the output device is busy it is processing the data. Normally when the software writes data to an output port, that only starts the output process. The time it takes an output device to process data is usually longer than the software execution time. When the output device is done, it is ready for new data. When the output device makes the transition from busy to ready, it releases the software to go forward.

In a similar way, when the software writes data to the output, it releases the output device hardware. The output interface illustrated in Figure 11.5 is also I/O bound because the time for the output device to process data is longer than the time for the software to generate and write it.

Again, I/O bound means the bandwidth is limited by the speed of the I/O hardware. The software must wait for the output device to finish the previous operation (I/O bound). The busy-wait solution for this output interface is also unbuffered, because when the hardware is done, it will wait for the software and after the software generates data, it waits for the hardware.

On the other hand, the interrupt solution (shown as the right part of Figure 11.2) is buffered, because the system allows the software to run continuously, filling a FIFO as fast as it wishes. In the same way, the hardware can empty the buffer whenever it is ready and whenever there is data in the FIFO. Again, FIFO queues allow the I/O interface to operate during both situations: I/O bound and CPU bound.

On some systems an interrupt will be generated on a hardware failure. Examples include power failure, temperature too high, memory failure, and mechanical tampering of secure systems. Usually, these events are extremely important and require immediate attention. The Cortex™-M processor will execute special software ( fault) when it tries to execute an illegal instruction, access an illegal memory location, or attempt an illegal I/O operation.

Universal Asynchronous Receiver Transmitter (UART) Video 12.2a. UART Background and Launchpad Support Video 12.2b. UART Operation In this section we will develop a simple device driver using the Universal Asynchronous Receiver/Transmitter (UART).

This serial port allows the microcontroller to communicate with devices such as other computers, printers, input sensors, and LCDs. Serial transmission involves sending one bit at a time, such that the data is spread out over time. The total number of bits transmitted per second is called the baud rate.

Serial Data Cable

The reciprocal of the baud rate is the bit time, which is the time to send one bit. Most microcontrollers have at least one UART. The LM4F120/TM4C123 has 8 UARTs. Before discussing the detailed operation on the TM4C, we will begin with general features common to all devices. Each UART will have a baud rate control register, which we use to select the transmission rate.

Each device is capable of creating its own serial clock with a transmission frequency approximately equal to the serial clock in the computer with which it is communicating. A frame is the smallest complete unit of serial transmission. Figure 11.6 plots the signal versus time on a serial port, showing a single frame, which includes a start bit (which is 0), 8 bits of data (least significant bit first), and a stop bit (which is 1). There is always only one start bit, but the Stellaris ® UARTs allow us to select the 5 to 8 data bits and 1 or 2 stop bits. The UART can add even, odd, or no parity bit. However, we will employ the typical protocol of 1 start bit, 8 data bits, no parity, and 1 stop bit. This protocol is used for both transmitting and receiving.

The information rate, or bandwidth, is defined as the amount of data or useful information transmitted per second. From Figure 11.6, we see that 10 bits are sent for every byte of usual data. Therefore, the bandwidth of the serial channel (in bytes/second) is the baud rate (in bits/sec) divided by 10. A serial data frame with 8-bit data, 1 start bit, 1 stop bit, and no parity bit.

Common Error: If you change the bus clock frequency without changing the baud rate register, the UART will operate at an incorrect baud rate. Checkpoint 11.1: Assuming the protocol drawn in Figure 11.6 and a baud rate of 1000 bits/sec, what is the bandwidth in bytes/sec? Table 11.1 shows the three most commonly used RS232 signals. The EIA-574 standard uses RS232 voltage levels and a DB9 connector that has only 9 pins.

The most commonly used signals of the full RS232 standard are available with the EIA-574 protocols. Only TxD, RxD, and SG are required to implement a simple bidirectional serial channel, thus the other signals are not shown (Figure 11.7). We define the data terminal equipment (DTE) as the computer or a terminal and the data communication equipment (DCE) as the modem or printer.

DB9 Pin EIA-574 Name Signal Description True DTE DCE 3 103 TxD Transmit Data -5.5V out in 2 104 RxD Receive Data -5.5V in out 5 102 SG Signal Ground Table 11.1. The commonly-used signals on the EIA-574 protocol. Hardware interface implementing an asynchronous RS232 channel.

The TM4C123 has eight UART ports. Observation: The LaunchPad sends UART0 channel through the USB cable, so the circuit shown in Figure 11.7 will not be needed. On the PC side of the cable, the serial channel becomes a virtual COM port.

Very-large-scale Integration

RS232 is a non-return-to-zero (NRZ) protocol with true signified as a voltage between -5 and ‑15 V. False is signified by a voltage between +5 and +15 V. A MAX3232 converter chip is used to translate between the +5.5/-5.5 V RS232 levels and the 0/+3.3 V digital levels. The capacitors in this circuit are important, because they form a charge pump used to create the ±5.5 voltages from the +3.3 V supply. The RS232 timing is generated automatically by the UART. During transmission, the MAX3232 translates a digital high on microcontroller side to -5.5V on the RS232/EIA‑574 cable, and a digital low is translated to +5.5V. During receiving, the MAX3232 translates negative voltages on RS232/EIA‑574 cable to a digital high on the microcontroller side, and a positive voltage is translated to a digital low.

The computer is classified as DTE, so its serial output is pin 3 in the EIA‑574 cable, and its serial input is pin 2 in the EIA‑574 cable. When connecting a DTE to another DTE, we use a cable with pins 2 and 3 crossed. I.e., pin 2 on one DTE is connected to pin 3 on the other DTE and pin 3 on one DTE is connected to pin 2 on the other DTE. When connecting a DTE to a DCE, then the cable passes the signals straight across.

In all situations, the grounds are connected together using the SG wire in the cable. This channel is classified as full-duplex, because transmission can occur in both directions simultaneously. Asynchronous Communication We will begin with transmission, because it is simple.

The transmitter portion of the UART includes a data output pin, with digital logic levels as drawn in the following interactive tool. The transmitter has a 16-element FIFO and a 10-bit shift register, which cannot be directly accessed by the programmer. The FIFO and shift register in the transmitter are separate from the FIFO and shift register associated with the receiver. In other words each UART has a receiver and a transmitter, but the interactive tool just shows the transmitter on one microcontroller and the receiver on the other.

To output data using the UART, the transmitter software will first check to make sure the transmit FIFO is not full (it will wait if TXFF is 1) and then write to the transmit data register (e.g., UART0DRR). The bits are shifted out in this order: start, b 0, b 1, b 2, b 3, b 4, b 5, b 6, b 7, and then stop, where b 0 is the LSB and b 7 is the MSB. The transmit data register is write only, which means the software can write to it (to start a new transmission) but cannot read from it. Even though the transmit data register is at the same address as the receive data register, the transmit and receive data registers are two separate registers. The transmission software can write to its data register if its TXFF (transmit FIFO full) flag is zero.

TXFF equal to zero means the FIFO is not full and has room. The receiving software can read from its data register if its RXFE (receive FIFO empty) flag is zero. RXFE equal to zero means the FIFO is not empty and has some data. While playing the following interactive tool, watch the behavior of the TXFF and RXFE flags. Interactive Tool 11.4 Use the following tool to watch the steps involved in Serial Communication of a simple two-byte message. Click Start/next over and over to single step the process, and click Run to run the entire sequence. Click Start to Send 'H' to the direction register.

When a new byte is written to UART0DRR, it is put into the transmit FIFO. Byte by byte, the UART gets data from the FIFO and loads them into the 10-bit transmit shift register. The 10-bit shift register includes a start bit, 8 data bits, and 1 stop bit. Then, the frame is shifted out one bit at a time at a rate specified by the baud rate register. If there are already data in the FIFO or in the shift register when the UART0DRR is written, the new frame will wait until the previous frames have been transmitted, before it too is transmitted. The FIFO guarantees the data are transmitted in the order they were written. The serial port hardware is actually controlled by a clock that is 16 times faster than the baud rate, referred to in the datasheet as Baud16.

When the data are being shifted out, the digital hardware in the UART counts 16 times in between changes to the U0Tx output line. The software can actually write 16 bytes to the UART0DRR, and the hardware will send them all one at a time in the proper order. This FIFO reduces the software response time requirements of the operating system to service the serial port hardware. Unfortunately, it does complicate the hardware/software timing. At 9600 bits/sec, it takes 1.04 ms to send a frame.

Therefore, there will be a delay ranging from 1.04 and 16.7 ms between writing to the data register and the completion of the data transmission. This delay depends on how much data are already in the FIFO at the time the software writes to UART0DRR. Receiving data frames is a little trickier than transmission because we have to synchronize the receive shift register with the incoming data.

The receiver portion of the UART includes a U0Rx data input pin with digital logic levels. At the input of the microcontroller, true is 3.3V and false is 0V. There is also a 16-element FIFO and a 10-bit shift register, which cannot be directly accessed by the programmer (shown on the right side of the interactive tool). The receive shift register is 10 bits wide, but the FIFO is 12 bits, 8 bits of data and 4 error flags. Again the receive shift register and receive FIFO are separate from those in the transmitter. The receive data register, UART0DRR, is read only, which means write operations to this address have no effect on this register (recall write operations activate the transmitter).

The receiver obviously cannot start a transmission, but it recognizes a new frame by its start bit. The bits are shifted in using the same order as the transmitter shifted them out: start, b 0, b 1, b 2, b 3, b 4, b 5, b 6, b 7, and then stop. There are six status bits generated by receiver activity. The Receive FIFO empty flag, RXFE, is clear when new input data are in the receive FIFO. When the software reads from UART0DRR, data are removed from the FIFO. When the FIFO becomes empty, the RXFE flag will be set, meaning there are no more input data. There are other flags associated with the receiver.

There is a Receive FIFO full flag RXFF, which is set when the FIFO is full. There are four status bits associated with each byte of data. For this reason, the receive FIFO is 12 bits wide.

The overrun error, OE, is set when input data are lost because the FIFO is full and more input frames are arriving at the receiver. An overrun error is caused when the receiver interface latency is too large. The break error, BE, is set when the input is held low for more than a frame.

Parity is a mechanism to send one extra bit so the receiver can detect if there were any errors in transmission. With even parity the number of 1's in the data plus parity will be an even number. The PE bit is set on a parity error. Because the error rate is so low, most systems do not implement parity. We will not use parity in this class. The framing error, FE, is set when the stop bit is incorrect. Framing errors are probably caused by a mismatch in baud rate.

The receiver waits for the 1 to 0 edge signifying a start bit, then shifts in 10 bits of data one at a time from the U0Rx line. The internal clock is 16 times faster than the baud rate. After the 1 to 0 edge, the receiver waits 8 internal clocks and samples the start bit. 16 internal clocks later it samples b 0.

Every 16 internal clocks it samples another bit until it reaches the stop bit. The UART needs an internal clock faster than the baud rate so it can wait the half a bit time between the 1 to 0 edge beginning the start bit and the middle of the bit window needed for sampling. The start and stop bits are removed (checked for framing errors), the 8 bits of data and 4 bits of status are put into the receive FIFO. The hardware FIFO implements buffering so data is safely stored in the receiver hardware if the software is performing other tasks while data is arriving. Observation: If the receiving UART device has a baud rate mismatch of more than 5%, then a framing error can occur when the stop bit is incorrectly captured. An overrun occurs when there are 16 elements in the receive FIFO, and a 17 th frame comes into the receiver. In order to avoid overrun, we can design a real-time system, i.e., one with a maximum latency.

The latency of a UART receiver is the delay between the time when new data arrives in the receiver ( RXFE=0) and the time the software reads the data register. If the latency is always less than 160 bit times, then overrun will never occur. Observation: With a serial port that has a shift register and one data register (no FIFO buffering), the latency requirement of the input interface is the time it takes to transmit one data frame.

TM4C UART Details Next we will overview the specific UART functions on the TM4C microcontroller. This section is intended to supplement rather than replace the Texas Instruments manuals. When designing systems with any I/O module, you must also refer to the reference manual of your specific microcontroller. It is also good design practice to review the errata for your microcontroller to see if any quirks (mistakes) exist in your microcontroller that might apply to the system you are designing. Stellaris TM4C microcontrollers have eight UARTs. The specific port pins used to implement the UARTs vary from one chip to the next.

To find which pins your microcontroller uses, you will need to consult its datasheet. Table 11.2 shows some of the registers for the UART0 and UART1. For the other UARTs, the register names will replace the 0 with a 1 – 7. For the exact register addresses, you should include the appropriate header file (e.g., tm4c123gh6pm.h). To activate a UART you will need to turn on the UART clock in the RCGC1 register.

You should also turn on the clock for the digital port in the RCGC2 register. You need to enable the transmit and receive pins as digital signals. The alternative function for these pins must also be selected. In particular we set bits in both the AFSEL and PCTL registers. The OE, BE, PE, and FE are error flags associated with the receiver. You can see these flags in two places: associated with each data byte in UART0DRR or as a separate error register in UART0RSRR. The overrun error ( OE) is set if data has been lost because the input driver latency is too long.

BE is a break error, meaning the other device has sent a break. PE is a parity error (however, we will not be using parity). The framing error ( FE) will get set if the baud rates do not match.

The software can clear these four error flags by writing any value to UART0RSRR. The status of the two FIFOs can be seen in the UART0FRR register. The BUSY flag is set while the transmitter still has unsent bits, even if the transmitter is disabled. It will become zero when the transmit FIFO is empty and the last stop bit has been sent.

If you implement busy-wait output by first outputting then waiting for BUSY to become 0 (right flowchart of Figure 11.10), then the routine will write new data and return after that particular data has been completely transmitted. The UART0CTLR control register contains the bits that turn on the UART. TXE is the Transmitter Enable bit, and RXE is the Receiver Enable bit.

We set TXE, RXE, and UARTEN equal to 1 in order to activate the UART device. However, we should clear UARTEN during the initialization sequence.

31–12 11 10 9 8 7–0 Name $4000.C000 OE BE PE FE DATA UART0DRR 31–3 3 2 1 0 $4000.C004 OE BE PE FE UART0RSRR 31–8 7 6 5 4 3 2–0 $4000.C018 TXFE RXFF TXFF RXFE BUSY UART0FRR 31–16 15–0 $4000.C024 DIVINT UART0IBRDR 31–6 5–0 $4000.C028 DIVFRAC UART0FBRDR 7 6 – 5 4 3 2 1 0 $4000.C02C SPS WPEN FEN STP2 EPS PEN BRK UART0LCRHR 31–10 9 8 7 6–3 2 1 0 $4000.C030 RXE TXE LBE SIRLP SIREN UARTEN UART0CTLR 31–12 11 10 9 8 7–0 $4000.D000 OE.

Has one USB-UART connector. To learn how to build UART communication between the FPGA board and the data terminal equipment (DTE) like computer terminal, I build two projects - UART transmitter and UART receiver. Part I focuses on the UART transmitter. We will transmit 8 bits data from Basys 3 to computers through USB-UART connector on Basys 3. When users turn on / off any switch, this form a binary value of an ASCII character. A byte (8 bits) character will be transmitted through the UART to the computer.

The character will show in the terminal (Terterm). All transmission is triggered when a button is pressed. Step 1: Step 1: UART Concept.

Reg 3:0bitcounter - 4 bits counter to count if 10 bits data transmission complete or not reg 3:0counter - 14 bits counter to count the baud rate reg 1:0state - Initial state variable for Mealy State Machine reg 1:0nextstate - Next state variable for Mealy State Machine reg 9:0rightshiftreg - 10 bits data needed to be shifted out during transmission. For storing the serial package and sending its bits one by one.

When the load signal is 1, it is loaded with a new character to transmit (8 bits). The least significant bit is initialized with the binary value “0” (a start bit) A binary value “1” is introduced in the most significant bit reg shift - Signal to show shifting data is ready reg load - Signal to show loading data is ready reg clear - Signal to clear all signals Step 5: Step 5: Baud Rate Generator. The master clock frequency on Basys 3 is 100MHz. We need baud rate of 9600 for UART transmission. To make a baud rate generator, we will use a counter. For example, the baud rate is only 9600 bits per second (bps).

Baud rate. counter = master clock frequency Therefore, we create a counter value is 10,416 for the baud rate of 9600. Counter = master clock frequency / baud rate When the counter for baud rate count up to 10415 (from 0 to 10415 = 10416) for a baud rate of 9600, we will reset the counter to be 0 and then change the state in the finite state machine.

In other words, the counter is used to slow down the 100MHZ FPGA clock for our program to work at 9600 baud. The reason for doing this is to make the program synchronous to the clock (or counter). Step 6: Step 6: Logic for Transmission. In step 5, we have created a counter for baud rate generator. Once the counter counts up to 10,416, check if clear, shift and load signals are asserted (“1”) one by one. I) If the load signal is asserted (“1”), the rightshiftregister loads the data that is to be transmitted and add start and stop bits.

This is why, once the state goes from IDLE to TRANSMIT, load goes high. It ensures that data is loaded into the register and is ready to be transmitted. Ii) If shift is asserted (“1”), rightshiftreg = rightshiftreg1. This shifts the data right one time.

Bitcounter is also incremented once. This tells the program that one bit was already sent. Iii) If clear is asserted (“1”), we have finished transmitting and bitcounter goes back to zero; waiting for another new transmission. We also create a synchronous Mealy State Machine 1.

IDLE State (S0): If the transmit is zero, we stay at the IDLE state and keep waiting until that button is pressed. Set load, shift and clear signals to 0. This prevent shifting when the transmission doesn’t start.

Do not set the bitcounter to zero. Otherwise, we can’t increment the bitcounter when we are transmitting the data. We do not have any data to load from just yet. TxD is held high to show that nothing is being transmitted (IDLE State).

We move to the TRNSMIT State when the input transmit is 1. This transmit is the push button on Basys 3 we press to tell the program we are going to transmit. Set the load to “1” (high) but keep shift and clear signal to be “0”(low). TRANSMIT State (S1): Remember, we have 8 data bits, 1 start bit and 1 stop bit.

When the bitcounter reaches 10 (equal or greater than 10), it means that it has completed its task of transmitting. When we reach our goal of a 10 bit transmission, the clear must be “1” (high) to clear the bitcounter back to zero and get ready for the next transmission. Also the next state must go back to IDLE. Keep load and shift to be “0” (low) If bitcounter is less than 10, we stay in TRANSMIT state. Also, we must put shift to 1 because we want to shift our rightshift register so the next bit can be shifted onto our TxD output pin for UART transmission.

This is done in TxD = shiftreg0. Load and shift are “0” (low).

Step 7: Step 7: Verilog Codes for Transmitter Module. To implement the design, we need to create constraints. Digilent provides master constraint file for. We need to do following tasks. Attached is the modified master constraint file. 1) uncomment pin we need by removing # in front of 'set property.'

In the top module, our inputs are 7:0 sw, so we go to switches and uncomment 'set property.' Statement from sw0 to sw7 2) change the signal name, e.g. We have two button inputs - btn0 and btn1. We will use the Logic Analyzer from See the attached picture for the set up.

Download the Digilent Waveforms at Attached is the Waveforms workspace with preset parameters. We will debug the following signals.

Set the time base to at least 100ms/div. You can also set the trigger of each signal. 1) Master clock- debugclk (JA4) 2) TxD- debugTxD (JA1) 3) transmit - debugtransmit (JA2) 4) button - debugbutton (JA3) Once you click 'Run' in the Logic Analyzer and then push the button on board. You will see the timing diagram and analyze the logic. The root cause for the debouncing is because of the longer period for transmit signal. (see picture).